Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0 . 18 m or lower : 1 . timing convergence problem seriously affects the circuits schedule , and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay . 2 . si problem , usually it consists two aspects of ir - drop and crosstalk . these problems often affect the chip function after tapout 本篇论文就是针对超深亚微米阶段soc芯片后端设计所面临的挑战,提出了运用连续收敛的布局布线策略,尤其是虚拟原型的设计理论,来快速验证布局,进而提高布线的成功率,并且提出了一种改进的布局评估模型,提高对soc芯片预测布线的准确度;同时,对于时钟驱动元件选择,文中提出了一种基于正态分布模型来达到更有效的选取。
It ' s suitable for the design of chips that has high performance and large needs . the approach includes system design , logic synthesis , simulation , placement and routing , and etc . as an example , the design process of an asic for frequency measuring is discussed detailed to show how to use this approach quickly and successfully 该方法包括系统设计、逻辑综合、仿真、布局布线等top - down的asic设计步骤。论文以asic测频芯片的设计过程为例，详细分析讨论了定制法的各个设计环节，以实际的设计过程论证各个设计环节，并且解决了在各个设计环节中遇到的问题：可测性设计的考虑、布局布线的考虑等。
The main work includes the deep study of microprocessor theory , the system - level design of the soft core that is performed based on it , the system function definition and partition , the design of all the functional modules . after completing system - level and algorithm - level designs , the rtl implementations of each module are performed and the functional simulation and fpga verification are carried out on the rtl codes . at last , the rtl codes are synthesized with synopsys " design compiler and the gat - level netlist is gotten 具体工作包括对微处理器理论的深入研究，并在此基础上完成16位risc微处理器软核16rmpu的系统级设计，实现系统功能定义和系统划分；完成软核各个模块的算法级设计和rtl级设计，并对软核的rtl级代码进行仿真和fpga验证；对软核进行dc ( designcompiler )综合，生成后端布局布线所需要的网表文件，最终实现微处理器软核的设计。
On one hand , the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data , have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data , on the other hand , interface focal point that circuit design transmission of data , part this finish mainly and interface of linkport of dsp , make data transmisst to dsp processor at a high speed , go on follow - up punish 一方面，接口电路设计的重点在于对天线数据的整理排队，采用了双端口ram配合计数器实现数据的排队，另一方面，接口电路设计的重点是数据的传输，这部分主要完成和dsp的linkport的接口，使数据高速传给dsp处理器，进行后续处理。这个项目按照自上而下的设计流程，从系统划分、编写代码、 rtl仿真、综合、布局布线，到fpga实现。
This dissertation finishes the design of pci bus target controller , with vhdl description of register transfers level . and it has also completed the function simulation as well as timing simulation after placing & routing . a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand 本论文完成了pci总线目标设备控制器的设计，采用vhdl对其进行了rtl级的描述，并且通过编写测试激励程序完成了功能仿真，以及布局布线后的时序仿真，通过fpga在pcb实验板上进行硬件仿真，证明所实现的pci目标设备控制器符合基本功能要求。
Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller . this dissertation finishes the design of pci bus controller , and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last 通过本论文的研究,完成了pci总线控制器的设计,并且通过编写测试激励程序完成了总线控制器功能仿真,以及布局布线后的时序仿真,并设计了pcb实验板进行了测试,证明所实现的pci目标控制器完成了要求的功能。
Then has analysed function 、 port joining 、 inside structure of every module , etc . in detail . using hardware description language to program for function implementation , after function simulation 、 synthesis 、 place and route 、 timing simulation and download , the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx . all procedure of design is worked under the ise 6 . 2 integrated environment 接着详细分析了各模块的功能、端口连接、内部结构等,并利用硬件描述语言编写源代码实现各模块功能,经过功能仿真、综合、布局布线、时序仿真、下载等一系列步骤,最终在xilinx的spartan3系列xc3s400 - 4pq208芯片上实现。
