On the one hand , the size of the problem is enormous . for example , there are more than several million transistors in a single chip . on the other hand , along with the technique developing , the typical wiring width has arrived the deep sub micron stage ; the frequency has been ghz level 集成电路版图综合、设计验证是一个极其复杂的问题，一方面是由于版图综合、验证问题的规模庞大，例如目前单片vlsi包含的晶体管数已达几千万甚至上亿个个，另一方面是由于工艺的不断发展，版图特征线宽已发展到深亚微米阶段，芯片工作频率已达ghz级，对版图布局布线提出了更多的约束条件和目标，设计验证需要考虑更多的电路参数和复杂的相互作用。
Chapter 5 gives the design illumination of the rs coder and decoder based on fpga . then it gives the integrated results for realization design of the rs ( 31 , 15 ) error - correcting code . after that , it gives the functional and layout simulation results for the limited field multiplier , divider , rs coder and rs de - coder 第五章给出了基于fpga实现的rs编码器和译码器设计说明, rs ( 31 , 15 )纠错码设计实现的综合结果,有限域乘法器、除法器、 rs编码器、 rs译码器的功能仿真和布局布线后仿真结果,最后总结主要的调试经验。
Besides , we use software smooth filtering to minish the influence of white noise and high - frequency noise , ground connection and shield technology to eliminate electromagnetic interference , and rational circuit distribution to attain high signal - to - noise of the whole fiber optic weak magnetic sensor system 另外,采用软件平滑滤波等处理以减小白噪声和高频噪声的影响,利用接地及屏蔽技术消除外界的电磁干扰,并对电路进行合理布局布线,以获得高信噪比的光纤微弱磁场传感器系统。
Mostly , this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then , choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation 设计主要采用menter公司的功能强大的fpgaadvantage作为开发工具，进行了各个层次、各个模块的设计输入、仿真以及逻辑综合，完成了电路的前端设计；然后选用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，进行布局布线，然后再进行时序仿真，生成配置文件。
On the other hand , we accomplished the asic design flow successfully based on the fpga design . we have made the most use of various optimization methodology and simulation tools include dynamic simulation , static timing analyzing and post simulation . at last this design net list was past to layout design team in order to check its electronic characters 在我们的asic流程中,首要的因素是在fpga验证其正确性的基础上对速度与面积进行科学有效的平衡,在成本和性能中间取得良好的结合点,运用先进的eda设计工具和算法对设计进行综合优化( synthesis ) ,动态时序分析( dynamicsimulation ) ,静态时序仿真( sta )到自动布局布线( apr )之后将寄生参数反标回前面的步骤进行更精确的判断和分析,最后交给版图设计人员进行版图设计和优化。
In the pcs design the anti - interference and signal integrity of high - speed mixed - signal circuit are taken into consideration . some eda software are used here to simulate the circuit before and after the place & route . all of these make the design correct in the first time 电路板设计则综合考虑了数模混合pcb的抗干扰性、高速电路的信号完整性等问题，同样在eda环境下进行了布局布线前后的仿真验证工作，使设计真正达到了设计即正确，确保了一次设计成功，大大降低了设计成本。
The logic design of interface circuit is realized in verilog hardware description language ( hdl ) . function simulation is finished by modelsim software . after the synthesis , placing , routing and obtaining delay information by develop tool quartus ii4 . 0 , timing simulation is accomplished by modelsim software 接口电路的逻辑设计采用硬件描述语言veriloghdl ,先借助modelsim软件进行功能仿真验证,在quartusii4 . 0的集成开发环境中完成综合、布局布线并提取元器件和网线上的实际延迟信息后,再借助modelsim软件进行时序仿真验证。
There are several aspects of work that was done in this thesis mainly . firstly , the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed . secondly , decoding circuit of the under - water long - range remote control system was designed with fpga , including vhdl coding , simulation , synthesis , place & route , etc . besides , power consumption to fpga that is designed is estimated in this thesis . lastly , we designed and made one pcb to verify and test fpga decoding chip that is designed , and debugged and tested it finally 首先，深入研究和分析了在频域实现水下远程遥控解码的原理并进行了遥控指令编码设计；其次，用altera公司的cyclone系列fpga芯片完成了水下远程遥控fpga解码芯片的设计工作，包括硬件描述语言( vhdl )编码、电路前后仿真、综合和布局布线工作，并对设计的fpga解码芯片进行了初步的功耗估算；最后设计制作了一块fpga解码芯片电路验证测试板，并完成了电路调试和测试。
This thesis analyzes the system ’ s architectures of hardware and software , emphasizes on introducing the hardware development process including the design methods of each circuit module in detail . at last , after solving the problems of high speed printed circuit board ( pcb ) layout , realize the wireless access system ’ s pcb 本文分析了基于ieee802 . 11b无线局域网的无线接入系统的软硬件的结构,着重介绍了硬件电路的开发流程,以及各部分电路模块的具体设计方法,最后在解决了高速印制电路板( printedcircuitboard )设计中的布局布线问题以后,制作出了无线接入系统的pcb 。
The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl 在innoveda的visualhdl设计平台上用hdl语言完成了设计输入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler进行了基于alterafpga库的网表综合，最后将edif网表输入altera的布局布线工具quartus中进行了布局布线，将生成的sdo文件反标到modelsim仿真器中进行了时序仿真，该设计的成功，再一次表明了hdl设计方法的正确性和有效性。
