The design phase includes the standardization of rtl coding , logic synthesis and place & route ; the verification phase includes the function verification , static timing analysis and physical verification for 08c01 设计工作包括对08c01软核的rtl级代码标准化、逻辑综合和布局布线；验证工作包括对08c01软核的功能验证、静态时序分析和物理验证。
The project of developing the core comes from a national key program in science and technologies , study on mcu high level language description and embeded system technology . the project is followed the top - down design way 这个项目遵循了自上而下的设计流程，从系统划分、编写代码、 rtl仿真、综合、门级仿真，到布局布线、电气规则检查、设计规则检查，网表比较等。
The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively 布局布线后结果表明本文所设计的rs编码器的速度可达到66mhz ；解码速度可达到47mhz ，电路规模为4 . 6万门，包含有3 . 2k的内部缓存fifo的rs编/解码电路。
This paper is clued by the design and implementation of fpga and asic , and it expatiates on the subject of pci bus target controller , which involves all processes of design , simulation , synthesis and test , placing and routing 以fpga和asic的设计和实现为线索，阐述了pci总线目标设备控制器设计、仿真、综合验证及布局布线的各个步骤，以及基于asic技术的高层次设计方法。
The ip core ’ s synthesis , place & route were based on develop tool quartusii4 . 2 . the timing simulation was based on modelsim . at last , the ip was downloaded to altera ’ s fpga for real - time simulation and test 选用硬件描述语言veriloghdl进行电路设计,在开发工具quartusii4 . 2中完成软核的综合、布局布线,在modelsim中进行时序仿真验证,并下载到altera公司的cyclone系列fpga中进行验证测试。
In chapter 5 , design methods of the digital control circuits are introduced . further more , sensor dynamic range adjustment methods are also introduced . in chapter 6 , measurement and results are introduced and analysis a 第五章主要介绍了通过数字电路设计方法（ verilog语言描述， synopsys软件综合， cadencese自动布局布线）进行数字控制电路设计的方法以及传感器感光动态范围调整的设计考虑。
We use different commercial eda tools in order to achieve better implementation in different design phase , which include silicon ensemble of cadence , design compiler and design primer of synopsys and so on 在设计的不同阶段使用了不同的主流eda工具进行辅助设计和验证，包括synopsys公司的逻辑综合工具designcompiler 、静态时序分析工具designprimer和cadence公司的自动布局布线工具siliconensemble等。
Then the general platform hardware will be cut out and integrated , all of the circuits and the pcb will be designed and realized . the design process of pcb needs to follow the idea of high speed circuit layout , otherwise the pcb can ’ t work any more 之后,在此平台上进行硬件的裁剪与集成,设计和实现无线接入系统的硬件电路,最后制作出pcb ,其中pcb的制作要依据高速pcb的布局布线的思想进行,才能保证系统正常工作。
2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path 我们采用90纳米cmos标准单元工艺以及synopsys自动布局布线流程进行实验，实验结果表明该算法在高性能双通路结构的浮点加减运算中引入后，可以使得近路径的运算延迟整体降低10 . 2 % ，且算法本身没有造成新的关键路径。
The commonly used designing flow and basic technology of integrated circuit , such as the cell layout , synthesis , simulation , fpga verification , automatic layout & routing of the digital circuit , are introduced and analyzed in detail . the layout designing and simulation of the analog circuit are also introduced and analyzed in detail 论文对集成电路常用设计流程和基本技术作了详细介绍和分析，其中包括数字电路的基本单元版图、综合、仿真、 fpga验证和自动布局布线，也包括常用模拟电路的版图设计和仿真。
