除法器的英文

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"除法器"怎么读用"除法器"造句

英文翻译手机版

divider

"除法"英文翻译 division
"器"英文翻译 implement; utensil; ware
"乘法除法器" 英文翻译 : multiplication division unit; multiplication-division unit
"程序除法器" 英文翻译 : program divider; programmed divider
"除法器，分割器" 英文翻译 : divider
"除法器电路" 英文翻译 : divider circuit
"电子除法器" 英文翻译 : electronic divider
"对数除法器" 英文翻译 : logarithmic divider
"剪取除法器" 英文翻译 : clipping divider
"模拟除法器" 英文翻译 : analog divider; analogue divider
"十进除法器" 英文翻译 : decade divider
"数字除法器" 英文翻译 : digital divider
"移位除法器" 英文翻译 : shifted divider
"乘法器除法器部件" 英文翻译 : multiplier divider unit
"除法器两脚规" 英文翻译 : divider compasses; dividers
"二进制除法器" 英文翻译 : binary divider
"分压器除法器" 英文翻译 : dividend
"可编程除法器" 英文翻译 : programmable divider
"模拟量除法器" 英文翻译 : analog divider
"三进制除法器" 英文翻译 : ternary divider
"十进制除法器" 英文翻译 : decade divider
"可编程序除法器" 英文翻译 : programmable divider
"除法" 英文翻译 : division
"法器" 英文翻译 : [宗教] musical instruments used in a buddhist or taoist mass
"擦除法" 英文翻译 : eraser

例句与用法

Abstract : this paper introduces a new power factor meter with sample hod circuit and divider and provides basic measurment circuit . experiment result proves the practicality of the power factor meter
文摘:本文介绍了利用采样保持器和除法器实现的功率因数测量仪表，给出了测量电路原理图，实验结果表明了该测量仪表的实用性。
The number of error symbols that can be corrected by the decoder is 2 . the design process includes storing the input data , calculating the syndromes , designing multiplier and divider and solving the key equation
Rs （ 256 ， 252 ）译码器的设计过程主要包括输入数据的存储、伴随式的计算、乘法器和除法器的设计、关键方程的求解等几个步骤。
Then we show an algorithm design of the elliptic curve crypto based on galois field . as a main part , the design theory and concrete solution of it are presented step by step , ic chip design method for implementation of the algorithm is described in detail
设计完成了一种基于有限域的椭圆曲线加密算法，主要包括适合于168bit椭圆曲线加密的有限域乘法、加法、除法器的实现； 4
Chapter 5 gives the design illumination of the rs coder and decoder based on fpga . then it gives the integrated results for realization design of the rs ( 31 , 15 ) error - correcting code . after that , it gives the functional and layout simulation results for the limited field multiplier , divider , rs coder and rs de - coder
第五章给出了基于fpga实现的rs编码器和译码器设计说明, rs ( 31 , 15 )纠错码设计实现的综合结果,有限域乘法器、除法器、 rs编码器、 rs译码器的功能仿真和布局布线后仿真结果,最后总结主要的调试经验。
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的结构，针对嵌入式应用具有以下特点：采用分离的指令和数据cache （哈佛结构），五级流水，硬件乘法器和除法器，中断控制器， 16位的i / o端口和灵活的内存控制器，具有较强的异常处理功能，新模块可以轻松的通过片上的ambaahb / apb总线添加。