门延迟的英文

• gate delay

• "门"英文翻译    entrance; exit; door; gate
• "延迟"英文翻译    delay; lag; defer; postpone; ...
• "门延迟时间" 英文翻译 :    gdt gate delay time
• "气门延迟关闭" 英文翻译 :    late closing of valve
• "进气门延迟开闭发动机" 英文翻译 :    livc late intake-valve-closing
• "进气门延迟开闭系统" 英文翻译 :    litv late intake-valve closing
• "延迟" 英文翻译 :    delay; lag; defer; postpone; put off; hold over; retard 将这件事延迟到下次会上讨论 hold the matter over till the next meeting; 展览会开幕的日期延迟了。 the opening of the exhibition has been postponed.; 延迟报警 delayed alarm; 延迟计数器 delay counter; 延迟继电器 delayed relay; 延迟装置 deferred mount; [电学] delayed action device; time-lag device;延迟自动增益控制[电学] delayed automatic gain control
• "群延迟, 组延迟" 英文翻译 :    group delay
• "包线；延迟" 英文翻译 :    envelope delay
• "包延迟" 英文翻译 :    packet delay
• "纯延迟" 英文翻译 :    pure delay
• "粗延迟" 英文翻译 :    coarse delay
• "耽误，延迟" 英文翻译 :    delay
• "蝶延迟" 英文翻译 :    adjusted delay
• "断延迟" 英文翻译 :    off delay
• "光延迟" 英文翻译 :    light delay
• "核延迟" 英文翻译 :    nuclear delay
• "将……延迟" 英文翻译 :    hold sth．over
• "零延迟" 英文翻译 :    zero delay; zero-lag
• "码延迟" 英文翻译 :    code delay
• "群延迟" 英文翻译 :    envelope delay; group delay; grouretardation
• "热延迟" 英文翻译 :    heat lag
• "声延迟" 英文翻译 :    acoustic delay
• "湿延迟" 英文翻译 :    wet delay
• "使延迟" 英文翻译 :    detain

• When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
  在深亚微米制造技术中，芯片互连线延迟超过门延迟，而且随着集成电路工作频率的提高，允许的时序容差变小，传输延迟的影响加大，设计工作难度增加。
• An algorithm of path - based timing optimization by buffer insertion is presented . the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation . and heuristic method of buffer insertion is presented to reduce delay . the algorithm is tested by industral circuit case . experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
  提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束

• 门延迟的日语：ゲートディレイ