缓冲器插入的英文

• buffer insertion

• "缓冲器"英文翻译    buffer; dead block; antifluc ...
• "插入"英文翻译    insert; infix; run in; break ...
• "缓冲器" 英文翻译 :    buffer; dead block; antifluctuator; bumper; compression bumper; counterbuff; dashpot relay; impact damper; vibroshock; snubber; cushion; anti-fluctuator; beam; amortisseur◇缓冲器活塞 buffering piston
• "寄存器插入" 英文翻译 :    register insertion
• "缓冲剂；缓冲器" 英文翻译 :    buffer
• "缓冲器，缓冲区" 英文翻译 :    buf buffer
• "缓冲器；缓冲剂" 英文翻译 :    buffer
• "缓冲区，缓冲器" 英文翻译 :    buffer
• "缓冲；缓冲剂；缓冲器" 英文翻译 :    buffer
• "ommaya贮器插入术" 英文翻译 :    insertion of ommaya reservoir
• "rickham贮器插入术" 英文翻译 :    insertion of rickham reservoir
• "放大器插入架" 英文翻译 :    amplifier nesting unit
• "寄存器插入环" 英文翻译 :    register insertion ring
• "武器插入面板" 英文翻译 :    weapon insert panel
• "缓冲；缓冲器；减震器" 英文翻译 :    buffer
• "减震，缓冲缓冲器" 英文翻译 :    buffer
• "半字缓冲器" 英文翻译 :    half word buffer; half-word buffer
• "保险杠，缓冲器" 英文翻译 :    bumper
• "备用缓冲器" 英文翻译 :    standby buffer
• "比特缓冲器" 英文翻译 :    bit buffer unit
• "变换缓冲器" 英文翻译 :    mapped buffer
• "变址缓冲器" 英文翻译 :    index buffer
• "兵乓缓冲器" 英文翻译 :    ping-pong buffering
• "并行缓冲器" 英文翻译 :    parallel buffer
• "操作缓冲器" 英文翻译 :    operation buffer

• Path - based timing optimization by buffer insertion with accurate delay model
  采用精确时延模型基于路径的缓冲器插入时延优化
• An algorithm of path - based timing optimization by buffer insertion is presented . the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation . and heuristic method of buffer insertion is presented to reduce delay . the algorithm is tested by industral circuit case . experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
  提出了一种基于路径的缓冲器插入时延优化算法,算法采用高阶模型估计连线时延,用基于查表的非线性时延模型估计门延迟.在基于路径的时延分析基础上,提出了缓冲器插入的时延优化启发式算法.工业测试实例实验表明,该算法能够有效地优化电路时延,满足时延约束
• Abstract : an algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented . given a two - terminal net , the algorithm can minimize the total number of buffers inserted to meet the delay constraint . a high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look - up table is for buffer delay estimation . the experimental results show that the algorithm can efficiently achieve the trade - offs between number of buffers and delay , and avoid needless power and area cost . the running time is satisfactory
  文摘:提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的