浮点单元的英文

• fpu floating point unit

• "浮点"英文翻译    floating decimal; floating p ...
• "单元"英文翻译    unit; unit element; cell; lo ...
• "浮点单元〖处理器" 英文翻译 :    fpu floating point unit
• "共深度点单元" 英文翻译 :    cdp-cell
• "浮点处理单元" 英文翻译 :    floating process unit; floating-point unit (fpu); fpu: floating-point processing unit
• "浮点运算单元" 英文翻译 :    floating point unit
• "浮点执行单元" 英文翻译 :    floating point execution unit
• "浮点" 英文翻译 :    [计算机] floating decimal; floating point
• "材料盘点单" 英文翻译 :    stores inventory sheet
• "点单步法" 英文翻译 :    point single step method
• "多点单播" 英文翻译 :    multipoint-unicast
• "盘点单输出" 英文翻译 :    stock take check list printing
• "重点单位" 英文翻译 :    key unit
• "斑点单轴搪瓷" 英文翻译 :    granite ware
• "有点单纯复形" 英文翻译 :    pointed simplicial complex
• "浮点乘" 英文翻译 :    floating multiply
• "浮点除" 英文翻译 :    floating divide
• "浮点法" 英文翻译 :    floating point
• "浮点基" 英文翻译 :    floating-point basis
• "浮点机" 英文翻译 :    floating-point machine
• "浮点加" 英文翻译 :    floating add
• "浮点减" 英文翻译 :    floating subtract
• "浮点阶" 英文翻译 :    floating-point exponent
• "浮点数" 英文翻译 :    floating number; floating point numbers; floatingpoint numberk; gleitkommazahl floating-point number; specfloat
• "浮点型" 英文翻译 :    float point type; float type; floating type; floating-point types

• Resets the floating - point unit ( fpu ) , if any
  有浮点单元（ fpu ）的话，将其重置。
• In the project , the microprocessor is composed of integer unit and floating - point unit
  本课题所设计的微处理器共包括两部分：整数单元和浮点单元。
• Function ensures the rounding mode of the floating - point unit is toward zero truncate , by setting bits 10 and 11 of the control word
  函数还通过设置控制字的第10位和第11位来确保浮点单元( fpu )的舍入模式为向零方向（截断） 。
• There are five parts in powerpc603e ? microprocessor : integer execution unit , floating point unit ( fpu ) , instruction ( data ) cache , bus interface unit and memory manage unit . the instructions are executed with pipeline way
  Powerpc603e微处理器系统由定点执行单元、浮点单元、指令(数据) cache 、总线接口单元、存储管理单元组成，以流水和超标量方式执行指令。
• Different with traditional microprocessor which solves floating - point normalization with soft ware , the project implemented floating - point normalization with hard ware . the research focused on the architecture of microprocessor mainly
  因本课题意在实现微处理器的基本结构，并未涉及到编译器，因此在对微处理器的浮点处理单元的规格化算法进行深入分析的基础上提出了用硬件实现浮点单元规格化的方法。
• It has five parts , such as integer execution unit , floating point unit ( fpu ) , instruction cache , bus interface unit and memory manage unit . the instructions are executed with pipeline way . the instruction set and i / o signals are compatible with powerpc
  它由定点执行单元、浮点单元、指令cache 、总线接口单元、存储管理单元组成，以流水和超标量方式执行指令，指令集和接口时序兼容powerpc ，是典型的risc微处理器结构。
• To decrease the area of the chip , resource sharing , which is a synthesized optimized method of eda tools , was used in the project . the code was verified in fpga soft ware environment . synthesized netlists based on fpga and asic were given in the paper for future work
  本课题所设计的微处理器的整数单元和浮点单元均采用硬件描述语言vhdl进行建模，为降低芯片面积，将资源共享这一eda工具的综合优化方法应用于设计中，并在现有条件下进行了简单的fpga验证，考虑到今后的asic设计，本文给出了基于fpga和基于asic的两种综合网表。
• According to the task and delay information of the floating - point unit , it was implemented with three - stage pipeline , including pre - normalization stage , calculation stage and post - normalization stage . approximately , the delay of each stage is equal with each other . also , floating - addition , floating - subtraction and floating - multiplication can been implemented by the floating - point unit
  根据浮点单元承担的任务及延迟信息，采用三级流线实现：前规格化级( pre - normalizationstage ) 、计算级( calculationstage ) 、后规格化级( post - normalizationstage ) ，每一级的工作量和延迟近似相等。