浮点加法器的英文

• floating point adder
• floating-point adder

• "浮点"英文翻译    floating decimal; floating p ...
• "加法"英文翻译    addition; additive
• "器"英文翻译    implement; utensil; ware
• "浮点加" 英文翻译 :    floating add
• "加法器" 英文翻译 :    adder (addr); adding box; adding device; adding machine; count detector; summation meter; summator; summer; summing unit; totaliser; totalizer; totaller
• "浮点加速器" 英文翻译 :    fpa floating-point accelerator
• "浮点减法器" 英文翻译 :    floating point subtracter; floating-point subtractor
• "八位加法器" 英文翻译 :    eight bit adder
• "半加法器" 英文翻译 :    half adder; half-adder; one-column adder; one-digit adder; single-digit adder; two-input adder
• "编码加法器" 英文翻译 :    coded adder
• "变址加法器" 英文翻译 :    index adder
• "并行加法器" 英文翻译 :    parallel adder; ripple carry adder
• "穿孔加法器" 英文翻译 :    perforating adder
• "串联加法器" 英文翻译 :    serial type adder; series type adder
• "串行加法器" 英文翻译 :    serial adder; serialadder
• "代数加法器" 英文翻译 :    algebraic adder
• "地址加法器" 英文翻译 :    aad address adder; address adder
• "电加法器" 英文翻译 :    electrical adder
• "二进加法器" 英文翻译 :    binary adder; binaryadder
• "幅度加法器" 英文翻译 :    ammplitude adder; amplitude adder; amplitude contraction
• "符合加法器" 英文翻译 :    coincidence adder
• "负加法器" 英文翻译 :    soft adder
• "高速加法器" 英文翻译 :    high speed adder
• "高位加法器" 英文翻译 :    left-hand adder
• "红色加法器" 英文翻译 :    red adder

• The product rule is very simple and easy to implement , and it does n ' t increase additional delay
  该“产生式规则”简单而易以实现，而且不增加浮点加法器的延迟。
• The data and conclusions prove that these designs are better than the original ones ; the floating - point adder is really optimized
  实验证明这些设计的性能都比原有设计有所提高，达到了优化浮点加法器的目的。
• The main research area is the structure optimization of floating - point adder , which is intent to minimize the delay of floating - point addition and optimize the circuit structure
  主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
• The author is absorbed in research on technology of coprocessor design . in the floating - point addition the paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading - zero logic circuits , considering algorithm and construction of logic circuits . an approach of micro program controller design for coprocessor is put forward and a test bench is given to verify its function
  笔者研究协处理器的设计技术，在浮点加法器中提出动态与静态结合设计进位链的方案以及前导零预测面积与速度的折衷方法；在微程序控制器的设计中提出一种协处理器微程序控制器的设计方法，并且给出其功能验证的测试平台。
• The primary contents and innovations of this article are introduced below . in order to take advantage of the high speed of calculation , and at the same time , improve the accuracy and dynamic - range of the algorithm , three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format . the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure
  论文的主要工作及创新点如下:为了充分利用fpga处理速度快的特点,同时尽量提高算法的精度及动态范围,本文在对浮点加法器算法进行深入研究的基础上,规纳总结了三种不同的多输入浮点加法器算法,并创造性地提出了一种高效的多输入浮点加法器结构及一种适合于fpga实现的自定义浮点数格式,这种高效的结构在所需的逻辑资源和运算速度上均远优于传统的多输入结构。