总线时序的英文

• bus timing

• "总线"英文翻译    highway; bus; trunk
• "时序"英文翻译    sequence; sequential; time s ...
• "总线时序仿真" 英文翻译 :    bus-timing emulation; bustiming emulationn
• "总线时钟" 英文翻译 :    bclk bus clock
• "总线时钟频率" 英文翻译 :    bus clock rate
• "总线时钟，总线定时" 英文翻译 :    bclk bus clock; bus clock
• "总线接口时序" 英文翻译 :    bus interface timing
• "时序" 英文翻译 :    [地质学] sequence; sequential; time sequence; timing sequence; sequence in time
• "占线时" 英文翻译 :    if busy
• "总线" 英文翻译 :    highway; bus; trunk
• "总线，总线" 英文翻译 :    bus
• "布线时项差" 英文翻译 :    wiring skew
• "点线时标" 英文翻译 :    dotted line marker
• "基线时间" 英文翻译 :    base time; baseline time
• "接线时间" 英文翻译 :    setting up time
• "上线时爱你" 英文翻译 :    yuniko
• "射线时间" 英文翻译 :    raytime
• "虚线时标" 英文翻译 :    dotted line marker
• "寻线时间" 英文翻译 :    hunting time
• "在线时间" 英文翻译 :    online time
• "直线时基" 英文翻译 :    linear time base
• "直线时基管" 英文翻译 :    line-time base valve
• "非时序" 英文翻译 :    non-sequential
• "时序表" 英文翻译 :    time scale; time-scale
• "时序的" 英文翻译 :    sequential

• During the design of vxi - bus serial controller module , the functions of vxi - bus including time - sequence for vxi interface , resource management , interrupt process , bus arbitration , are accomplished . to advance the performance and stability , the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence , the uart , the parameterized baud generator and “ pipeling frame ” . the handle type of data transfer bus for vxi - bus is researched thoroughly , and the format of serial data transfer is designed
  在vxi总线串行控制器设计中,实现了vxi总线控制器的基本功能,包括vxi总线接口时序、总线仲裁、超时处理等;同时利用先进的fpga技术实现了串行总线时序向vxi总线时序的转换、通用异步收发器( uart ) 、参数化波特率发生器、流水线结构等功能模块;在设计中还深入研究了vxi总线数据传输的各种操作类型,制定了串行数据传输的编码格式。
• The subject has mainly finished designing and debugging software and hardware of a / d decode module , fpga video processing module , video data frame deposit module , base clock produce module , d / a encode module , i2c bus control module , etc . a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
  本课题主要完成了a d解码模块、 fpga视频处理模块、视频数据帧存模块、基准时钟产生模块、 d a编码模块、 i ~ 2c总线控制模块等部分软、硬件设计及调试。其中a d解码模块采集模拟电视信号实现视频解码； fpga视频处理模块对解码后的数据进行去噪处理的同时还负责系统的逻辑控制；视频数据帧存模块为大量高速的视频数据提供缓冲区；基准时钟产生模块通过输入基准视频信号为系统提供精确的相关同步信号； d a编码模块在视频处理模块的控制下把数字视频数据转换成复合电视信号供显示用： i ~ 2c总线控制模块模拟i ~ 2c总线时序实现对系统中编、解码芯片的初始化。