基准电路的英文

• reference circuit

• "基准"英文翻译    datum standard; criterion; r ...
• "电路"英文翻译    circuit; electric circuit; e ...
• "基准电压电路" 英文翻译 :    lm336-5v
• "假设基准电路" 英文翻译 :    hypothetical reference circuit
• "基准电压电路1" 英文翻译 :    lm337t
• "白基准电平" 英文翻译 :    white reference level
• "基准电池" 英文翻译 :    reference battery
• "基准电极" 英文翻译 :    reference electrode
• "基准电流" 英文翻译 :    background current; reference current
• "基准电平" 英文翻译 :    datum level; reference level
• "基准电平点" 英文翻译 :    reference level point
• "基准电桥" 英文翻译 :    reference bridge
• "基准电位" 英文翻译 :    reference potential
• "基准电压" 英文翻译 :    generator for reference voltage; reference potential; votage reference
• "基准电压管" 英文翻译 :    voltage reference tube
• "基准电压源" 英文翻译 :    reference voltage source
• "基准电源" 英文翻译 :    reference power supply
• "基准电阻" 英文翻译 :    reference resistance
• "标准电路" 英文翻译 :    preferred circuit; standard circuit
• "调准电路" 英文翻译 :    alignment circuit
• "校准电路" 英文翻译 :    calibrated circuit; calibrating circuit; calibration circuit; scaling circuit
• "已批准电路" 英文翻译 :    approved circuit
• "参考基准电位" 英文翻译 :    reference potential
• "甘汞基准电极" 英文翻译 :    calomel reference electrode
• "黑色基准电平" 英文翻译 :    black reference level

• Hypothetical reference circuit
  假设基准电路
• Combining the popular chopper modulate technology , the design of low offset reference circuit was put forward after in - depth analysis of the offset mechanics
  深入剖析了电路的失调机理,结合目前流行的斩波调制技术,设计了低失调基准电路。
• To cancel the offset - voltage of the comparator , a switch capacitance circuit is used between the three pre - amplifier stages . the charge pump circuit is used to boost the clock voltage of the switch transistor
  采用电荷泵电路提供开关管栅过驱动电压，带隙基准电路作为电荷泵稳定电压的输入，有利于改善开关电路的性能。
• Since high performance control logics are usually hard for non - scan test generation , dft structures could be embedded as offsets in tradition , while it will cause manufacturing cost increase and performance overhead . in this paper , an indirect test generation method based on retiming is proposed , which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes . experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic
  对性能驱动控制逻辑进行测试生成难度较大，通常要加入可测性结构，但会影响原电路优化性能并增加生产成本.本文以重定时理论为基础，提出了对高性能时序电路进行间接测试生成的方法，这种方法在不影响原电路任何优化特性的前提下，可显著降低测试生成时间，提高测试生成质量.在iscas ’ 89部分基准电路进行实验，结果证明了其有效性
• The traditional bandgap reference circuit was improved in the design , which includes the applying of self - bias structure and cascode structure , output of the opamp was used as self - bias voltage , saving bias circuit , and then it was helpful to get low power consumption . through using poly resistance of high value with low temperature coefficient , we reduced the influnce to circuit , if power supply did not change , we must decrease operating current to decrease power consumption , and increasing value of resistor could decrease the operating current efficiently . poly resistance of high value had large value of squared resistor , so we could save layout area
  对传统带隙基准电路进行了改进设计,采用自偏置结构和镜像电流镜结构,利用运放的输出电压作为运放的偏置电压,节省了偏置电路,降低了功耗;使用低温度系数的多晶硅高值电阻,降低了电阻温漂对电路的影响;在电源电压不变的情况下,为了减小功耗就必须减小工作电流,而增大电阻的阻值能有效地减小工作电流,多晶硅高值电阻的方块电阻很大,可以节省版图面积。