基准时钟的英文

• rc reference clock

• "基准"英文翻译    datum standard; criterion; r ...
• "时钟"英文翻译    clock
• "主基准时钟" 英文翻译 :    prc primary reference clockk; primary reference clock
• "铷基准时钟" 英文翻译 :    rubidium master reference clock
• "地区基准时钟" 英文翻译 :    lprc local primary reference clocks
• "基准时钟电源" 英文翻译 :    vco
• "基准时钟模块" 英文翻译 :    rcm reference clock module
• "外部基准时钟" 英文翻译 :    external reference clock
• "区域基准时钟源" 英文翻译 :    local primary reference lpr
• "一级基准时钟源" 英文翻译 :    primary reference clock
• "本地基本参照时钟，地区基准时钟" 英文翻译 :    lprc local primary reference clocks
• "标准时钟" 英文翻译 :    standard time clock
• "基准时间" 英文翻译 :    base time; fiducial time; reference time; time origin
• "基准时间法" 英文翻译 :    fiducial time method
• "时钟基准板" 英文翻译 :    clock reference board cki
• "基准时间修正" 英文翻译 :    fiducial time corrections
• "节目时钟基准" 英文翻译 :    pcr: program clock reference
• "系统时钟基准" 英文翻译 :    scr system clock reference
• "单基准时间服务器" 英文翻译 :    single reference time server
• "基准时间服务器" 英文翻译 :    reference time server
• "基准主时钟及从时钟" 英文翻译 :    primary reference and slave clocks
• "基本码流时钟基准" 英文翻译 :    escr: elementary stream clock reference
• "准时" 英文翻译 :    punctual; on time; on schedule 火车准时到达。 the train arrived on schedule. 请准时出席。 please be punctual. 尽管下雨, 他还是准时到了。 he was there on the stroke in spite of the rain
• "电话机制造和标准时钟表公司" 英文翻译 :    telefonbau und normalzeit gmbh
• "时钟计时员按计划准时到港的定期船" 英文翻译 :    time-keeper

• Local primary reference lpr
  区域基准时钟源
• Primary reference clock pr
  主基准时钟
• The tft lcm driver signals were enable signal and fiducial clock signal , which were strict with synchronization
  驱动信号主要为使能信号和基准时钟信号,并要求二者具有严格的同步性。
• All circuit undergoes simulation , accord with the design requirement , the test results of the whole pll circuit validate our specifications
  全部电路经模拟,完全满足设计要求,可以作为加速度计中数字测频电路的基准时钟。
• A monolithic clock synthesis pll , which is expected to be a reference 800mhz clock generator in accelerometer system , has been designed and characterized in this paper
  本文设计了一种采用锁相环频率合成技术实现的800mhz时钟发生器,用作加速度传感器读出电路的基准时钟信号。
• Single frequency source is usually used as local oscillator in communication system and radar system , also as a reference clock in digital circuits , so it is a extensive - applied technique
  固定频率源可以在在通讯系统和雷达系统中作为本机振荡器,也可以作为数字电路的基准时钟信号,因此得到了广泛的应用。
• In its digital processing circuit , clock chip with high precision and temperature compensation is uesd as reference clock . high frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes saw signals are selected timely by multichannel selector
  数字信号处理电路采用高精度、具有温度补偿的时钟芯片作为基准时钟，采用高频可逆计数器对整形后的脉冲信号进行正向或逆向计数，采用高性能的多路选择器控制两路saw信号的定时选择。
• Second , this dissertation implements separately a mpeg - 2 video decoder and a dolby ac - 3 digital audio decoder based on software mode , and gives a audio & video synchronization algorithm based on audio - clock - benchmark in mpeg - 2 system decoder , whose feasibility and practicability have been proved by experimenting . it is an all - purpose algorithm , which can perform different decoder according to mpeg - 1 or mpeg - 2 system models , and can also be used for reference to the implementation of other multiplex stream decoders
  然后，论文实现了基于软件方式的mpeg - 2标准视频及ac - 3格式压缩音频的实时解码与回放，并依据mpeg - 2系统解码模型实现了一种基于音频基准时钟的mpeg解码器的视音频同步算法，实验证明该算法可行、实用、通用性好，对符合mpeg - 1或mpeg - 2系统标准的视音频解码器均具适用性。
• The subject has mainly finished designing and debugging software and hardware of a / d decode module , fpga video processing module , video data frame deposit module , base clock produce module , d / a encode module , i2c bus control module , etc . a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
  本课题主要完成了a d解码模块、 fpga视频处理模块、视频数据帧存模块、基准时钟产生模块、 d a编码模块、 i ~ 2c总线控制模块等部分软、硬件设计及调试。其中a d解码模块采集模拟电视信号实现视频解码； fpga视频处理模块对解码后的数据进行去噪处理的同时还负责系统的逻辑控制；视频数据帧存模块为大量高速的视频数据提供缓冲区；基准时钟产生模块通过输入基准视频信号为系统提供精确的相关同步信号； d a编码模块在视频处理模块的控制下把数字视频数据转换成复合电视信号供显示用： i ~ 2c总线控制模块模拟i ~ 2c总线时序实现对系统中编、解码芯片的初始化。

• 基准时钟的日语：きじゅんとけい