分接器的英文

• coupler
• demultiplexer
• muldex

• "分接"英文翻译    shunting; tap off; tapping; ...
• "器"英文翻译    implement; utensil; ware
• "复分接器" 英文翻译 :    mux multiplexer/demultiplexer
• "数字分接器" 英文翻译 :    digital demultiplexer
• "网络分接器" 英文翻译 :    network taps
• "复接器和分接器" 英文翻译 :    multiplexer and demultiplexer
• "分接" 英文翻译 :    [电学] shunting; tap off; tapping; branch-off◇分接电容器 bridging condenser;shunting condenser;分接点tapping point; 分接开关 tap changer
• "半分接" 英文翻译 :    half tap
• "分接点" 英文翻译 :    take off point; tapping point
• "分接级" 英文翻译 :    tapping step
• "分接区" 英文翻译 :    tapping zone
• "分接头" 英文翻译 :    tap◇分接头电压 tap voltage; 分接头晶体 [电子学] tap crystal; 分接头控制 tapped control; 分接头切换装置 changer; 分接头调节 tapped control
• "分接线" 英文翻译 :    extension wire
• "光分接" 英文翻译 :    ot optical tapoff
• "热分接" 英文翻译 :    hot-tapping
• "螺丝攻,分接,分接头" 英文翻译 :    tap
• "部分接触" 英文翻译 :    partial contact
• "部分接地" 英文翻译 :    partial earth contact; partial earthing; partial ground
• "部分接合" 英文翻译 :    partial conjugation
• "部分接合子" 英文翻译 :    merozygote; syngenote
• "部分接线图" 英文翻译 :    partial wiring diagram
• "差分接口" 英文翻译 :    differential interface
• "充分接收机" 英文翻译 :    sufficient receiver
• "磁场分接" 英文翻译 :    field tapping
• "电缆分接点" 英文翻译 :    cable distribution point

• Development of quartic group demultiplexer for digital communication
  数字通信四次群分接器的研制
• According to the requirements of the project and the solution design , clinux is selected as the os of sdh adm control platform
  结合本课题的要求及方案设计,确定clinux作为sdh专用分接器控制平台的嵌入式操作系统。
• The dissertation ’ s emphasis is on the research of a sdh multiplexer which can be used in specific field of sdh transmission network
  本论文主要研究满足特定应用场合要求的sdh分接器,属于sdh网元,在此称为sdh专用分接器。
• Firstly , the sdh equipment architecture which itu - t recommends and the specific requirement of the project are analysed in the dissertation
  论文先根据itu - t制定的sdh设备功能划分标准和项目的具体指标,设计了sdh专用分接器的系统方案。
• Therefore , it can be named by “ the specific demultiplexer of sdh ” . the design of pos line card was discussed and we also have finished the control logic of the hardware platform of the specific demultiplexer
  论文主要讨论专用分接器的pos线卡设计和硬件平台的控制逻辑电路设计与实现。论文首先对基于fpga的10gbps的pos线卡的设计方案进行了研究。
• Three basic strctures for demultiplexer , i . e . serial , parallel and tree . their working principal , advantages and disadvantages will be discussed in the thesis . according to their characteristics and the design objective . the tree architecture was selected
  根据三种结构的各自特点和设计目标，选用树型结构作为分接器的基本结构。电路设计是分接器设计的基础。
• In order to reduce the cost and cubage , the realization method of “ the specific demultiplexer of sdh ” is difference from other sdh facilities . so it can be applied in some situation
  为了降低设备的成本和体积、简化配置,本论文使用了不同于大型通信设备提供商研发sdh设备的思路,可以做到低成本、小体积、配置简便,因此sdh专用分接器在某些环境必能得到更有效的应用。
• In this dissertation , the principle of sdh is introduced at first . then the function of “ the specific demultiplexer of sdh ” is analyzed . after confirming the logic function blocks , the hardware architecture and the stm - 1 module and ds3 module are designed
  论文首先介绍了sdh的原理,然后分析技术指标,在确定了sdh专用分接器的逻辑功能块组成后,提出了硬件的总体架构和子模块划分,并对stm - 1模块和ds3模块的实现可行性进行分析。
• Circuit design is the basis of design of demultiplexer . speed , power and chip area are the main factors that should be considered in circuit design . every circuit structure has its merits and drawbacks , e . g . cmos logic family has a slower speed , but lower power , smaller area , scfl ( source couple fet logic ) family has a higher speed , but higher power , larger area . we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors . flip - flop is the fundamental element of demultiplexer , setup time and hold up time are key factors , which influence the speed of circuit , thus the design aim is how to reduce them . in this thesis we place emphasis on the design of scfl latches
  速度、功耗、面积是电路设计要考虑的主要因素，不同的电路形式具有不同的优缺点，如cmos互补逻辑电路功耗低，面积小，速度相对较慢； scfl (源极耦合fet逻辑)电路速度高，功耗和面积较大。所以要针对具体设计需要选用适当的电路形式或其组合结构，以满足设计要求。触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了scfl锁存器的设计和优化方法。