保持电路的英文
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"保持电路"怎么读用"保持电路"造句
英文翻译手机版
- hold circuit
- holding circuit
- locking circuit
- retaining circuit
- "保持"英文翻译 keep; hold; retain; maintain ...
- "电路"英文翻译 circuit; electric circuit; e ...
- "自保持电路" 英文翻译 : self-hold circuit
- "采样保持电路" 英文翻译 : sampling hold circuit
- "抽样保持电路" 英文翻译 : sample and hold circuit; sample hold circuit; sample-and-hold circuit; sampled-hold circuit
- "峰值保持电路" 英文翻译 : peak hold circuit; peak holding circuit
- "跟踪保持电路" 英文翻译 : track and hold circuit
- "进路保持电路" 英文翻译 : route holding circuit
- "零阶保持电路" 英文翻译 : zero order hold
- "取样保持电路" 英文翻译 : sample-and-hold
- "同步保持电路" 英文翻译 : synchrolock
- "置位保持电路" 英文翻译 : set-hold circuit
- "最小保持电路" 英文翻译 : minimum hold circuit
- "“与”逻辑保持电路" 英文翻译 : and hold circuit
- "矩形波串保持电路" 英文翻译 : boxcar hold circuit
- "脉冲抽样保持电路" 英文翻译 : pulse sample-and-hold circuit
- "保持电路强制同步电路" 英文翻译 : locking circuit
- "脉冲抽样和保持电路" 英文翻译 : pulse sample and circuit
- "脉冲试样和保持电路" 英文翻译 : pulse sample-and-hold circuit
- "保持电键" 英文翻译 : holding key
- "保持电流" 英文翻译 : holding current; keeper current; sealing current; sealingcurrent
- "保持电容器" 英文翻译 : hold capacitor
- "保持电压" 英文翻译 : keeper voltage; sustaining voltage
- "保持电源" 英文翻译 : kapwr kealive power; kapwr keealive power
- "保持电子枪" 英文翻译 : holding gun
例句与用法
- A kind of gain error correction scheme for sample - and - hold circuit
保持电路中的一种增益误差自校正方法 - The slope of inl is two more times than the slope of dnl
并将此技术用于所设计系统的分布式采样保持电路模块中。 - Sample and hold circuit
取样保持电路 - Track and hold circuit
跟踪保持电路 - Sampling hold circuit
取样保持电路 - Specification for performance requirements for cables required to maintain circuit integrity under fire conditions
在火灾情况下保持电路完好的电缆性能要求规范 - In front of the a / d converter in an analog conversion system is usually located a sample - and - hold circuit
在模拟量转换系统中在模/数转换器的前端通常都会有一个采样-保持电路。 - This paper introduced a practical pulse - width keeping circuit . this circuit has been used in a wide - band arm header
介绍了一种实用脉宽保持电路的实现,该电路已被用于宽带被动雷达导引头中。 - Compared to its commercial counterparts , the proposed scheme can improve the instruction throughput by 23 % , while maintaining the hardware and power consumption
实验表明,相比商业化的处理器,该策略下的超标量结构在保持电路和功耗开销的同时,指令吞吐率平均有23 %的提高。 - The sample and hold circuit is employed by the bottom plate sampling technique , which could not only cancel the charge injection error but also eliminate the effect of clock feed - through
采样保持电路设计采用了电容下极板采样技术,不仅有效地避免了电荷注入效应引起的采样信号失真,而且消除了时钟馈通效应的不良影响。
- 更多例句: 1 2
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