位并行的英文

• bit parallel
• bit-parallel
• parallel bit

• "位"英文翻译    place; location
• "并行"英文翻译    parallel; pairing; concurren ...
• "按位并行" 英文翻译 :    parallel by bit
• "将按位并行" 英文翻译 :    parallel-by-byte
• "位并行传输" 英文翻译 :    parallel bit transmission
• "计算机的位并行" 英文翻译 :    parallel-by-bit
• "位并行相联处理机" 英文翻译 :    bit parallel associative processor
• "位并行相联存储器" 英文翻译 :    bit-parallel a ociative memory; bit-parallel associative memory
• "位并行字符传送" 英文翻译 :    bit parallel character transfer
• "并行" 英文翻译 :    [计算机] parallel; pairing; concurrence; go side by side; run parallel
• "单位并矢式" 英文翻译 :    unit dyadic
• "单位并向量" 英文翻译 :    unit dyad
• "并行 并行运算" 英文翻译 :    parallel parallel operation
• "并行-并行逻辑" 英文翻译 :    parallel-parallel logic
• "并行的" 英文翻译 :    collateral; comitans; concurrent; paralleled; side-by-side
• "并行地" 英文翻译 :    concurrently
• "并行度" 英文翻译 :    degree of parallelism; parallelism
• "并行法" 英文翻译 :    parallel addition; parallel mode
• "并行管" 英文翻译 :    collateral ve el; collateral vessel; collateralve el; vasa collaterale
• "并行化" 英文翻译 :    deserializeparallelization; parallelization
• "并行机" 英文翻译 :    parallel machine
• "并行加" 英文翻译 :    parallel added
• "并行口" 英文翻译 :    epp/ecp; lpt port; parallel port
• "并行流" 英文翻译 :    parallel flow
• "并行式" 英文翻译 :    parallel mode

• Bit - parallel associative memory
  位并行相联存储器
• The data transfer capacity ( in bits per second ) of a bit - parallel bus
  每条位并行总线上可传输数据的容量,用比特秒表示。
• In this paper , we developed a self - assembly model for dna - based parallel addition . the central feature of this model is to apply the parallel logic . we make the complexity analysis of the algorithm used here
  这里，提出了一种利用dna进行两个数的相加的模型，这一模型的思想是对两数逐位并行相加，极大地利用了dna计算并行的特点。
• Based on the realization of the encoder / decoders , this scheme aims at the highest rate downstream frame , and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation . the fprme decoder is advanced in the world . the parallel fec circuit completely conforms to the itu - t protocols , and has important practical value
  在rs ( 255 , 239 )硬件编码器/解码器实现的基础上,本文按照gpon协议要求,针对gpon中最高速率2 . 488gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行fec编解码和解扰码电路,并作了仿真。
• The specific route is as follows : firstly , the output signals from the multipath sensor are nornalized , i . e . , all sensor signals ( including the analog data ) are transformed into multipath square wave pulse signals to form multipath parallel condition codes . these codes are treated as input signals for dac to obtain a series of dispersed analog signals for output as input signals for the vco . finally , a high frequency modulation signal is conducted at the vco ' s output
  具体技术路线如下：先将由多路传感器输出的信号进行归一化处理，即将所有传感器信号(包括模拟量)转换成多路方波脉冲信号，以形成多位并行信号的状态码，将其作为dac的数据输入信号，从而得到一系列离散的模拟信号输出，作为vco的输入信号，最终在vco输出端形成高频的调制信号。
• This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip , corresponding the mac sublayer of ethernet , to realize csma / cd media access protocol , manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface . 2 ) serdes ( serializing and deserializing ) chip , corresponding pcs and pma sublayers in ethernet , mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data , and convert them again at the receiving end . 3 ) fibre transceiver unit , completing light - electrical conversion of seri
  该网卡主要由3块集成的芯片完成其功能，分别是i ）网络控制主芯片，对应于以太网的mac子层，主要完成csmaicd介质访问协议，管理片上集成的发送和接收缓冲区，并提供和主板p0总线的接口： b ） s rd s （串行解串行化器）芯片，对应于以太同的pcs和pma子层，主要完成sb lob编码并将10位并行的数据转换为串行数据，在接收端完成相反的功能：涌）光纤收发器，完成串行数据的光电转换功能。

• 位并行的日语：ビットパラレル