串行器的英文

• serializer-deserializer (serdes)

• "串行"英文翻译    serial; tandem
• "器"英文翻译    implement; utensil; ware
• "串行器变换时钟" 英文翻译 :    clock, serializer shift; serializer shift clock
• "串行器 串化器 并串行转换器 并串转换器" 英文翻译 :    serializer
• "串行" 英文翻译 :    [计算机] [电学] serial; tandem
• "步行器" 英文翻译 :    walker; walking device
• "飞行器" 英文翻译 :    aerobat; air vehicle; beast; bird; flight vehicle
• "航行器" 英文翻译 :    aircraft
• "划行器" 英文翻译 :    marking gauge; marking gage; row marker
• "环行器" 英文翻译 :    microwave circulator
• "缓行器" 英文翻译 :    creeper attachment; creeper gear; creeperattachment; retarder
• "换行器" 英文翻译 :    shifter
• "执行器" 英文翻译 :    actu actuator; actuating apparatus; correcting unit; final controlling element,
• "指行器" 英文翻译 :    marker shoe; sighting marker
• "助行器" 英文翻译 :    isd-912l; isd-964; walking aid, walker
• "指行器 划行器铲" 英文翻译 :    markershoe
• "并串行" 英文翻译 :    [计算机] parallel series◇并串行计算机 parallel-serial computer; 并串行寄存器 paralled-serial register; 并串行式 parallel-series mode
• "串行的" 英文翻译 :    serial
• "串行舵" 英文翻译 :    tandem rudder
• "串行柜" 英文翻译 :    cascade tank
• "串行化" 英文翻译 :    serializable; serialization; serialize
• "串行机" 英文翻译 :    tandem engine
• "串行口" 英文翻译 :    serial port
• "串行流" 英文翻译 :    serial flow
• "串行数" 英文翻译 :    number serial; serial number

• The full chip can be partitioned to four modules , lvds driver , lvds receiver , serializer and deserializer . we implement these modules with different approaches based on their fuctions and characters
  芯片可划分为lvds驱动器、 lvds接收器、串行化器和解串行器四个模块。
• The marquee xml - rpc library contains many features i didn t discuss such as invocation pre - processors and serializers to translate java objects into structs for xml - rpc transmission
  Marquee xml - rpc库所包含的许多功能我都没有论述（如调用预处理器和串行器以将java对象转化为xml - rpc传输结构） 。
• The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach . the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures , and makes a lot of verilog simulation and verification on the circuits designed
  串并模块串行化器和解串行器采用标准单元的方法设计，论文讨论了对几种时钟同步模式以及串并转换电路结构的权衡和实现，并对所设计的电路结构进行了verilog模拟验证。

• 串行器的法语：sérialiseur