synopsys造句

• The flow of post - sim with synopsys nanosim amp; star - rcxt
  的晶体管级后仿真流程
• 2 . timing setup : load sdc ( synopsys design constraint ) file . define timing analysis options
  2 .在时序设置阶段,加入了时序约束,使整个设计在时序启动下完成。
• Synopsys ' s vera is one of the most modern languages designed specially for making testbenches
  其中， synopsys公司的vera语言是专用于设计测试平台的现代语言之一。
• After a brief description of asic design flow adopted by pci target secure chip , the thesis make great emphasis on various methods and skills used in physical design and verification with apollo ii from synopsys
  物理级设计：在对pci安全芯片所采用的的asic设计流程简单介绍后，文章重点论述了基于apollo的物理设计和验证方法和技巧。
• After evaluating synopsys ' s formality , the paper construes the flow and practical experiences in video post - process chip , and comes to the conclusion that static verification really works
  在简单评价了synopsys公司的商用软件formality之后，重点分析了在视频后处理芯片项目中formality的应用流程和实际工作经验，证明形式验证的重要作用。
• The test bench program is a virtual pci system , which comprise the microblaze model established from xilinx edk and also the pci / pci - x model from synopsys company . function level or gate level simulation can be done on this test bench
  测试平台中,利用xilinxedk生成的microbalze处理器仿真模型,以及synopsyspci / pci - xflexmodels模型组建了一个虚拟的pci系统,可进行门级和行为级的仿真。
• At last , we compile the design with synopsys design compiler in 0 . 25wn cmos technology . the synthesis information about area , power and time shows that this method has the advantage of fitting special architecture into algorithms easily
  最后用0 . 25 mcmos工艺在eda工具上实现，综合结果表明：基于ip核的软硬件协同设计方法，具有具体结构对算法的适应性好、设计周期短、系统易于优化等特点。
• We use different commercial eda tools in order to achieve better implementation in different design phase , which include silicon ensemble of cadence , design compiler and design primer of synopsys and so on
  在设计的不同阶段使用了不同的主流eda工具进行辅助设计和验证，包括synopsys公司的逻辑综合工具designcompiler 、静态时序分析工具designprimer和cadence公司的自动布局布线工具siliconensemble等。
• Then , a new design automation methodology is put forward which uses uml for specification , systmec for simulation and synopsys tools ( cocentric systemc compiler ) for hardware synthesis . the main feature of this methodology is its high possibility of implementation
  提出了一个基于uml系统描述的， systemc模拟验证的，利用cocentricsystemccomplier进行硬件综合的自动化设计方案，这个方案最大特点是可实现性强。
• Except for design methodology and technique , some comprehensive experiments are performed . these experiments use some eda tools , including functional simulation with cadence ' s verilog xl , logic synthesis with synopsys ' s design compiler
  本文除了介绍的设计方法和设计技巧，还做了一些有益的实验，使用到许多流行的eda工具，如cadence公司的verilog - xl 、 siliconensemble ， synopsys公司的designcompiler 、 physicalcompiler等。
• 2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path
  我们采用90纳米cmos标准单元工艺以及synopsys自动布局布线流程进行实验，实验结果表明该算法在高性能双通路结构的浮点加减运算中引入后，可以使得近路径的运算延迟整体降低10 . 2 % ，且算法本身没有造成新的关键路径。
• The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
  在innoveda的visualhdl设计平台上用hdl语言完成了设计输入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler进行了基于alterafpga库的网表综合，最后将edif网表输入altera的布局布线工具quartus中进行了布局布线，将生成的sdo文件反标到modelsim仿真器中进行了时序仿真，该设计的成功，再一次表明了hdl设计方法的正确性和有效性。
• 3 ) design switch system using eda based on the result of a11alysis . because the function of switch system is very complicated , some modules are designed by schematics directly , most modules are designed by verilog hdl using eda technology , synthesized by the synopsys software . at last a high speed atm switch system is designed , including voq as input buffer strategy dpa cell scheduling algorithm and crossbar switch fabric
  在前面分析的基础上根据目前的条件，对一个空分交换系统各模块进行前端设计和仿真，由于交换系统的功能复杂，我们一部分将采用直接画原理图的方法进行设计，大部分将采用集成电路设计自动化的方法进行设计，即采用硬件设计语言verilog ? hdl进行设计，用synopsys软件对设计进行综合，生成线路图，然后作门级电路仿真。
• This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
  该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。
• The main work includes the deep study of microprocessor theory , the system - level design of the soft core that is performed based on it , the system function definition and partition , the design of all the functional modules . after completing system - level and algorithm - level designs , the rtl implementations of each module are performed and the functional simulation and fpga verification are carried out on the rtl codes . at last , the rtl codes are synthesized with synopsys " design compiler and the gat - level netlist is gotten
  具体工作包括对微处理器理论的深入研究，并在此基础上完成16位risc微处理器软核16rmpu的系统级设计，实现系统功能定义和系统划分；完成软核各个模块的算法级设计和rtl级设计，并对软核的rtl级代码进行仿真和fpga验证；对软核进行dc ( designcompiler )综合，生成后端布局布线所需要的网表文件，最终实现微处理器软核的设计。
• Then , we use software hspice of synopsys to realize the inductor macromodel , and the circuit system responding to hysteresis mathematic model can be designed well , meantime , the method of building the macromodel lay technical foundation for other circuits design and that simulation results approach to real behaveior
  然后,利用synopsys公司的电路仿真软件hspice实现磁芯电感宏观模型,完成了与整个磁滞数学模型相对应的电路系统的设计,为其它电路系统的设计,以及仿真结果更接近实际工作情况奠定了良好的技术基础。
• Cadence and synopsys eda tools is applied as design tools of this design , and having front - end simulation with verilog _ xl of cadence , having back end application simulation with hspice of avanti . after design finished we had twice mpw order sequence , and the test result of the sample conform to the request of design
  本次设计是在cadence和synopsys等eda设计工具上完成的，并进行了前端的verilog _ xl功能仿真验证和后端hspice的器件模拟，在完成整个设计流程后先后进行了两次mpw投片，其样片的测试结果达到了设计要求。
• Then , the external interface , interface timing and data structure of dw8051 ip core are illustrated in detail according to mcs - 51 signal chip . afterwards , the peripheral modules have been framed and designed from system level to register - transmission - logic ( rtl ) level according to the ic card telephone application . finally , the logic synthesis methodology , static timing analysis strategy and prototype emulate are proposed and used for the analysis of simulation results
  论文的研究从soc的概述引入,介绍了soc的现状;其次,结合mcs - 51单片机,给出了synopsys公司的ip核dw8051的外部接口及接口时序和数据结构;然后,根据智能ic卡话机的应用需要,从系统级到寄存器传输级( rtl )对dw8051核的外围电路接口模块进行详细规划和设计;最后,详细给出了soc设计流程中的逻辑综合技术、静态时序分析技术和仿真测试方案,并将其运用到论文的研究工作之中,给出了相关仿真测试结果。
• In this thesis , we study viterbi decoding algorithm first , and analyze the structure of viterbi decoder , then based on them , present the front - end asic design of viterbi decoder . during the course of design , design - compiler of synopsys is applied as synthesis tool of the design , verilog - xl of cadence is applied as the simulation tool
  本论文首先对viterbi译码算法进行深入的研究，分析译码器的结构功能，然后对viterbi译码器进行asic前端设计，本次设计是以synopsys公司的design - compiler作为综合工具、以cadence公司的verilog - xl作为仿真验证工具进行的。
• Compared to cx , hardwarec and specc , systemc can be expected to be the standard language for hardware / software co - design and co - simulation because systemc has the great power on describing the hardware / software heterogeneous systems and it will continually develop and many virtual tools will appear under great support of many leading eda vendors . for example , cocentric systemc studio and cocentric systemc compiler are powerful tools provided now by the synopsys corporation
  相对于c ~ x ， hardwarec和specc来说， systemc的优势在于，其一它本身有很强大的软件硬件描述功能，其二由于有众多公司的支持，它的描述功能不断增强，其三是与它相关的支持软件系统的不断推出，例如， synopsys公司的模拟工具cocentricsystemcstudio和硬件综合工具cocentricsystemccomplier等。