netlists造句

• To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project . the code was verified in fpga soft ware environment . synthesized netlists based on fpga and asic were given in the paper for future work
  本课题所设计的微处理器的整数单元和浮点单元均采用硬件描述语言vhdl进行建模，为降低芯片面积，将资源共享这一eda工具的综合优化方法应用于设计中，并在现有条件下进行了简单的fpga验证，考虑到今后的asic设计，本文给出了基于fpga和基于asic的两种综合网表。
• The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda's visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing-simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
  在innoveda的visualhdl设计平台上用hdl语言完成了设计输入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler进行了基于alterafpga库的网表综合，最后将edif网表输入altera的布局布线工具quartus中进行了布局布线，将生成的sdo文件反标到modelsim仿真器中进行了时序仿真，该设计的成功，再一次表明了hdl设计方法的正确性和有效性。