Abstract : an algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented . given a two - terminal net , the algorithm can minimize the total number of buffers inserted to meet the delay constraint . a high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look - up table is for buffer delay estimation . the experimental results show that the algorithm can efficiently achieve the trade - offs between number of buffers and delay , and avoid needless power and area cost . the running time is satisfactory 文摘:提出了在精确时延模型下,满足时延约束的缓冲器数目最小化的算法.给出一个两端线网,该算法可以求出满足时延约束的最小缓冲器数目.运用高阶时延模型计算互连线的时延,运用基于查找表的非线性时延模型计算缓冲器的时延.实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延,在二者之间取得了较好的折中.算法的运行时间也是令人满意的
Then the ideal models ( dielectric isolation structure with high - voltage interconnection and without high - voltage interconnection ) are simulated by a 2d device simulator medici respectively . according to the simulation results , the two models ’ breakdown mechanism is analyzed and compared , and the influence of the isolated trench structure parameter on breakdown - voltage is studied , synchronously 借助二维数值仿真软件medici对理想模型(有、无高压互连线两种情况的介质隔离结构)进行仿真,分析其耐压机理,研究隔离槽参数(槽宽、槽内氧化层厚度)对击穿电压的影响。
When feature size comes to 0 . 35 m , interconnect delay has contributed 70 % to total delay . distribution of delay parameters lies on actual implementation of layout , which results in the fact that timing closure has become the chief problem . so synthesis technology must be based on timing to insure timing closure 特征尺寸进入0 . 35 m后，互连线延迟占到系统延迟的70以上，而延迟参数的分布又取决于版图的具体实现，导致时序收敛成为设计的首要问题，因此综合技术必须要基于时序，保证时序收敛。
Applying the theory of polygon expanding and shrinking , a new critical area calculation method for soft and hard faults is given . a total formula is presented by dividing vlsi interconnects into two parts , contacting and conducting path , to calculate its critical area . finally the effect of hard and soft fault of different size defect on circuits is given by calculating soft fault area of a 4x4 shift register 本文基于多边形膨胀收缩理论给出了一种新的软、硬故障关键面积计算方法，该方法首先将vlsi中的互连线分成导电通道和接触区两部分，然后分别计算其软、硬故障关键面积，最后将这两部分相加起来得到总的软硬故障关键面积。
However , some improvements have been made for the distributed rc model , the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region . so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance . according to this model , two cases , that is , cmos driving transmission line and interconnect line between chips have been analyzed 对传统的分布rc模型进行了改善，但随着互连向深亚微米级发展，寄生效应的影响尤其是电感的影响，必须考虑，因此建立新的rlc传输模型是很必要的，本文提出了这种新的互连模型，并对cmos驱动互连线和芯片之间互连两种情况进行了分析，验证了延时模型是可靠和精确的，并对延时的改善起到了指导作用。
Abstract : an algorithm to resolve the coupling effect problem is proposed during the cross point assignment ( cpa ) stage . in the algorithm , the priority queue concept and the rip - up and reroute strategy are combined to control crosstalk noise caused by interconnect coupling capacitance . first , the nets are arranged into different priority queues according to their weighted sum of their length and criticality . then , the cpa problem for one queue of nets is translated into a linear assignment problem . after the assignment of one queue of nets , a post - cpa checking routine is performed to check and rip up the net pairs which violate the crosstalk noise constraint and then push them into the next queue to be reassigned . the algorithm is tested by a set of bench mark examples , and the experimental results are promising 文摘:提出了一种在过点分配阶段解决噪声耦合效应问题的算法.该算法采用优先队列同拆线重布策略相结合的方法,控制由互连线耦合电容引起的串扰噪声.算法中,首先按照线长和约束限制,将线网划分到若干个优先队列中.然后,将每个优先队列的过点分配问题转换为线性分配问题.在完成一个线网队列的分配后,通过过点分配后处理过程检查串扰约束满足情况,对违反约束的线网对进行拆除,放入后续线网队列进行重新分配.实验数据表明,该算法能够取得好的效果
Abstract : a new interconnect network model for linear network reduction is presented . in this new model , the ports of the interconnect network are classified into two groups : active and passive ports . after the classification , some proprieties of the interconnect network are found to be redundant and pruned before reduction . for common interconnect networks , the scale of reduced models is smaller than 50 of the scale of previous works 文摘:给出了一种用于线性网络约简的高效互连线模型.在这个新模型中,互连线网络的端口被分为有源和无源两类.通过端口的分类,部分的冗余特性可以在约简之前被删减.使用这种模型,约简后线性网络的规模可以减小50以上
