故障覆盖率

• The conclusion is that by using ant algorithm , the fault coverage about near half standard circuits is best ; and the generation speed is very higher than strategate ' s
  与现有测试生成器相比，基于蚂蚁算法的测试矢量生成结果中，有近一半的标准电路获得了最高的故障覆盖率；在生成速度方面远高于strategate等算法。
• The dynamic power supply current ( iddt ) is a new window through which we can observe the switching activities in digital circuits . iddt testing methods make possible further increasing the fault coverage
  动态电流提供了一个观测电路内部开关性能的新的窗口，动态电流测试方法为进一步提高故障覆盖率提供了可能。
• The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66 % ) , but the fault coverage and time performance are lower than gate - level test generation
  实验数据表明分层测试产生算法能大大压缩电路测试集（约为66 ） ，而故障覆盖率有略微下降，时间性能也有些许降低。
• These new methods adopt the circuit information contained in the power supply line current to realize the fault diagnosis . it can increase the fault coverage , reduce testing cost and improve the quality and reliability of ics
  它通过从电源电流信号中提取有效的信息来进行故障诊断,能够提高故障覆盖率,降低测试成本并提高集成电路产品的质量与可靠性。
• In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result , the fault coverage is more than 96 %
  本文针对嵌入式微处理器estar1的结构特点，研究并实现了边界扫描、内部全扫描和内建自测试三种可测性设计技术，取得了良好的效果，故障覆盖率达到96以上。
• The ratio of fault covering has always been the focus of testing designer in dft for a long time . now a single chip contains all kinds of circuits , so to solve the problem of the ratio of fault covering is even harder than before
  长期以来在可测性设计阶段，故障覆盖率一直是测试设计关心的重要课题，如今在一个芯片中包含了如此多种类型的线路，更为解决测试覆盖率问题增加了难度。
• ( 2 ) we programmed a demo ' s software on microsoft visual c + + 6 . 0 for implementing the algorithms to judge the testability , get the minimum test set and take the fault efficiency of the circuits . the software successfully realizes these functions
  ( 2 )编写了一套基于des理论的电路测试的演示软件，实现了对被测电路的可测试性判断、故障覆盖率和最小测试集求取的算法，能够实现对电路测试的各项功能。
• 3 ) we programmed a demo ' s software of circuits " test and fault diagnosis on borland c + + builder . this software can realize these functions , such as judging the testability , getting the minimum test set , testing circuit quickly and making a fault diagnosis
  3 、利用borlandc + + builder语言编写了一套电路测试与诊断演示软件，能够实现对特定电路的可测性判断、故障覆盖率、快速测试和故障诊断等各项功能。
• 9 larsson e , peng z . an integrated framework for the design and optimization of soc test solutions . journal of electronic testing ; theory and applications jetta , special issue on plug - and - play test automation for system - on - a - chip , aug . 2002 , 18 : 385 - 400
  对于每个单独芯核，本文提出了一个计算伪随机向量和确定型测试向量最好组合的算法，该算法不但不违反存储器大小的约束，并且满足最小化测试时间的要求，同时还能达到最大的故障覆盖率。
• Internal scan is advanced for the difficulty of fixing the state of sequential circuit , can be divided into full - scan and partial - scan . in this paper we use full - scan according to the real circumstance of estarl and get high fault coverage with very little impact on the circuit
  本文根据estar1的实际情况，设计实现了全扫描结构，既得到了较高的故障覆盖率，又对电路的延迟和芯片面积影响很小(延迟时间增加0 . 3 ，芯片面积增加0 . 01 ) 。