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流水线操作的英文

发音:  
"流水线操作"怎么读用"流水线操作"造句

英文翻译手机手机版

  • pile line operation
  • pipe line operation
  • pipeline operation
  • stream line operation
  • streamline operation

例句与用法

  • Achieving the ability to streamline operations
    实现了流水线操作的功能。
  • One 1995 microprocessor uses this deeper pipeline to achieve a 300 - megahertz clock rate
    一台1995年生产的微处理器用这种更先进的流水线操作可达到300兆赫的时钟频率。
  • The pipelining paradox is that it takes the same amount of time to clean a single dirty sock by either method
    流水线操作的矛盾在于用任何一种方法洗一双袜子所用的时间相等。
  • Modem superscalar microprocessors try to perform anywhere from three to six instructions in each stage
    现代超标量体系结构的微处理器努力在流水线操作的每一步中完成三到六条命令。
  • We introduced advanced product lines and operation mode of japan , also possess many experience managers and skilled workers
    公司引进了日本先进的服装生产流水线操作模式,现拥有一批经验丰富的高素质管理队伍、技术过硬的生产员工。
  • In fact , assuming that each stage takes the same amount of time , the time saved by pipelining is proportional to the number of stages involved
    实际上,假设每一工作步骤花费的时间相同,流水线操作所节约的时间与有关工作步骤的数目成比例。
  • Pipelining , superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology , and if hopes are realized , parallel processing will join them
    在微处理器技术的发展中,流水线操作、超标量体系结构和高速缓冲内存储器仍将扮演着重要的角色。如果可能,平行处理方法也会加人。
  • Combining the principles of pipelining and parallelism of dsp with idct theory , we concentrate on the use of multiply - accumulate unit of mcf5272 by merging the operations of addition and multiplication , and realize two dimension of idct with one dimension of idct efficiently . testing shows the software meets the requirement of real - time decoder
    重点结合mcf5272的流水线操作和并行操作特征和反离散余弦变换算法原理,将的二维反离散余弦变换转换成8点的一维反离散余弦变换,利用乘法累加器合并加法运算和乘法运算高效快速地实现了反离散余弦变换算法。
  • The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
    详细的阐述了64位vegacpu的特点,阐述了eda技术和asic设计的主要流程,阐述了vegacpu流水线结构、流水线操作、流水线暂停和异常处理,虚拟指令地址的结构和产生, mmu结构,包括指令tlb结构和虚拟指令地址向物理指令地址的生成流程, cache结构,寻址原理和指令的写策略,指令高速缓存的寻址原理和结构,以及指令的获取流程。
用"流水线操作"造句  
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