Abstract : ： a technique for carriersynchronization of a digital modem is studied and the results of computer simulations are given . through comp arison of twokinds of phase estimator systems , it is shown that the combination of phase signal decision process and signal decoding processwill improve system performances obviously 文摘:分析了数字调制解调器载波同步技术，提供了计算机模拟测试的结果，并通过对两种不同鉴相器系统的性能比较，说明了把信号相位判断过程与信号解码过程结合，可使系统的性能得到明显改善。
The fourth , mainly talk about the phase noise in the pll , and discuss the specific affect on out put phase noise caused by different components in frequency synthesizer , such as mixer , amplifier , multipler , divider , oscillator , phase detector etc . the last part is about how to choice the natural frequency of pll in order to get the better performance in phase noise 第二章从锁相环的基本原理出发,介绍了锁相环的几个基本部件:鉴相器?环路滤波器和压控振荡器,对线性化锁相环进行了详细的分析,对数字锁相环做了详细的介绍,分析了锁相环的相位噪声模型,讨论了频综中的混频器
In this paper we also provide some experimental results to prove the feasibility of three dimensional range imaging , the reliability of correlative phase discriminator based on ccd , the practicability of range image receive system based on mcp image intensifier and the improvements of the system 并且通过一系列实验验证了正弦波与方波并行相关鉴相测距原理的可行性，基于ccd的并行相关鉴相器的可靠性，以及基于mcp像增强器和ccd摄像机的三维成像鉴相接收子系统的实用性。
Through all the works above , this paper summarizes the technique to analyse the phase - detector type circuits with orcad / pspice9 software , especially it ? function of parameter sweep and performance analysis ; summes up the ways and means to optimize phase - detector type circuits with orcadipspice9 ? optimizer module 通过上述工作，本论文总结了用orcad pspice9特别是其参数扫描和性能分析功能分析鉴相器一类电路的方法；概括出了用其优化模块optimizer和性能分析功能对鉴相器一类电路进行优化设计的步骤和思路。
The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector , a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively 论文的主要贡献为以下几个方面: 1 .针对传统鉴频鉴相器速度慢、功耗高的缺点,改进了单相时钟动态d触发器的结构,设计出了一种高速低功耗的鉴频鉴相器,在反馈回路上加入延迟单元,能有效的消除鉴相死区。
First , an analysis for the design of the impulse phase lock oscillate , which includes impulse phase detector the dielectric resonant oscillate etc . secondly , presents an analysis for the design of wide band balanced low noise amplifier . the last two part simplify the theory and the electrical characteristics of the sub harmonic mixer , and the mmvco 第一部分着重介绍了脉冲锁相源的工作原理(主要包括取样鉴相器和介质稳频的压控振荡器) ,并介绍了研制结果的性能指标;第二部分介绍了平衡式宽带低噪声放大器的基本理论
But its performance is as same as common pll at a 5v voltage . so the pll performance is better than other plls at a 5v voltage , especially in power consumption and frequency . finally , the improved pll circuit used in the frequency synthesizer is composed of the improved vco , phase / frequency detector and charge pump . hspice simulation results show that the pll performance is better than other plls implemented by other vco in the same cmos technology 综合以上的研究与设计,本文用所改进的压控振荡器、无死区鉴相器及电荷泵电路组成了用于频率合成的锁相环电路,并对此电路进行整体设计及仿真,结果表明其在锁定时间、频率范围、输出相位抖动及功耗方面具有较好的性能,且对提高锁相环频率合成器的整体性能有一定的作用。
The thesis describes a prototype fractional frequency synthesizer which is supported by a project granted by the ministry of science and technology of pr china . firstly , based on the principle of pll , this paper briefly describes three basic pll components : phase detector ( pd ) , low pass filter ( lpf ) , voltage controlled oscillators ( vco ) , analyzes the linearized pll and summaries the transfer functions of third - order pll with ideal intergrator filter respectively . based on a microwave vco , the single point frequency pll frequency ranging from 2 . 2 to 2 . 5ghz is developed 首先，从锁相环的基本理论、原理出发，分析了锁相环中的三个基本部件：鉴相器、环路滤波器和压控振荡器，此后，针对线性化锁相环进行了分析，研究了在使用比例积分滤波器时，三阶锁相环的环路参数计算；在电路实现时选用了lmx2353 ，在此基础上，完成了2 . 2 ~ 2 . 5ghz范围内的小数频率合成器设计。
In this paper , a pll frequency synthesizer working in l band is researched . at fist , we review the basic of phase lock loop and it ' s constituent part . after that the basic conception and design method of pll frequency synthesizer was introduced , especially introduced the charge pump pll frequency synthesizer in detail 本文是采用锁相原理设计的l波段频率合成器，首先对锁相环路的工作原理和基本组成部分进行了简单的介绍，然后介绍了锁相频率合成器的原理和设计方法，主要介绍了目前小型频率合成器产品中使用最广泛的由电荷泵数字鉴频鉴相器和无源环路滤波器构成的频率合成器。
The designs of the pfd , digital filter ocxo and fractional - n counter in the frequency synthesizer unit are discussed , based on the pll theory . in order to improve the precision of pll , some design methods of pfd are given , and its feasibility is validated by the fpga hardware implement 2 .在锁相理论指导下,第三章讨论了频率合成器设计中的鉴频鉴相器、数字滤波器、恒温压控振荡器和分频电路设计。为了进一步提高频率合成的精度,文中给出了提高鉴频鉴相器性能的一些设计思想,结合fpga的硬件设计验证了其可行性。
