The proposed 64 bits high performance alu is optimized at algorithm level , logic level , circuit level and layout level , and is implemented in 0 . 18 m cmos process . furthermore , the testing technique of the alu is discussed . this thesis mainly contributes to the following aspect : 1 文章从部件的算法、逻辑结构、电路参数、物理版图等多个层次进行设计优化,在0 . 18 mcmos工艺下实现了一款64位高性能算术逻辑部件,并对该部件的测试方法进行研究。
The model , in this case , is the high - level language program - which , like all useful models , hides irrelevant detail about the idiosyncrasies of the underlying computing technology such as internal word size , the numbers of accumulators and index registers , the type of alu , and so on 这种情况下，模式就是这个高级语言程序，它就像所有有用的模式那样，隐藏了潜在的计算技术特性上的相关细节（比如内存字符大小，累加器的个数，索引寄存器， alu算术逻辑单元类型等等） 。
At last they finished the compatible mcu core . this paper generally introduces the development of computer instruction system and then further analyzes the mcu architecture and its pipline characterization . then this paper illustrates the principle and design of every module and explains the operation of every instuction by analyzing the behavior of alu 本文先简要介绍了计算机指令系统的发展，然后深入分析了微控制器的组成架构以及指令的两级流水，接着详细论述了的各个功能模块的工作原理和电路的设计考虑，通过算术逻辑单元alu的深入分析来探究了每条指令在mcu中执行情况。
Using “ logical effort ” method to analyze the circuit ’ s critical path , and choose the optimized size of transistors in theory by this method . then , using sta technique simulates and analyzes the circuit to optimize transistors size further , and the circuit optimization arithmetic based on sta is gained . results proved that the optimization strategy of combining theory and practice have better effect 结果证明,这种理论与实际结合的优化策略具有较好的效果;三、典型条件下,所实现版图关键路径延时1 . 38ns ,平均功耗45 . 3mw ,版图面积0 . 05112mm2 ,达到了较小的延时、功耗和面积;四、针对所设计的算术逻辑部件,研究了一种独特的内建自测试方法,只需较少的测试向量就可实现该部件100 %的故障覆盖率,具有很高的效率和较低的代价。
