The system - controlled iir filter and fft were realized using fpga in this paper , and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter . in the same time , it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft . it is different to the normal method in the adoption of pipeline single dual ram for each stage 论文用fpga实现了系统的受控iir滤波器和fft部分，受控滤波器采用改进的流水线结构，运行速度得到了大幅度的提高，同时运用n点复数dft算法来计算2n点实数数据，在fpga中实现了基2的1024点复数fft ，同一般的实现不同，采用了流水线式的每级单个双口ram的方法，节省了ram的容量，经验证，该设计符合滤波器系统的要求。
The main tasks of this paper are as follows : ( 1 ) carries on the analysis to 32 - bit mips processor architecture and the mips five stages pipeline , and obtains the restriction factor of mips pipeline efficiency . and analyzed the feasibility of further enhancing the mips pipeline ’ s efficiency 本文的主要工作内容如下: ( 1 )对32位mips处理器的系统结构和mips现有的五级流水线结构进行分析,得出了mips流水线执行效率的瓶颈因素,并分析了进一步提高现有mips流水线执行效率的可行性。
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too 详细的阐述了64位vegacpu的特点，阐述了eda技术和asic设计的主要流程，阐述了vegacpu流水线结构、流水线操作、流水线暂停和异常处理，虚拟指令地址的结构和产生， mmu结构，包括指令tlb结构和虚拟指令地址向物理指令地址的生成流程， cache结构，寻址原理和指令的写策略，指令高速缓存的寻址原理和结构，以及指令的获取流程。
In this paper , the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced , and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm , reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail . based on the ribm algorithm , a modified structure and a pipelined decoder scheme are presented . a tradeoff has been made between the hardware complexities and decoding latency , thus this scheme gains significant improvement in hardware complexity and maximum fre - quency 本文简要介绍了有限域基本运算的算法和常用的rs编码算法,详细分析了改进后的euclid算法和改进后的bm算法,针对改进后的bm算法提出了一种流水线结构的译码器实现方案并改进了该算法的实现结构,在译码器复杂度和译码延时上作了折衷,降低了译码器的复杂度并提高了译码器的最高工作频率。
The papers in the analysis of the figures orthogonal frequency conversion technology basis , more traditional lut and cordic ( coordinate rotation digital computer ) , analysis of the superiority of the latter ; and the use of verilog programming to maxplus ii software for the simulation environment , conducted in fpga devices based on the structure of the cordic simulation of frequency conversion 本论文在分析数字正交下变频技术的基础上,比较了传统的查表法和基于cordic算法的结构,分析了后者的优越性;并用verilog编程,以maxplus软件为仿真环境,在fpga上进行了基于cordic算法流水线结构的下变频仿真。
