Simulations are executed in altera ’ s quartus ii environment with altera ’ s stratix family fpgas using verilog hdl after analysis . the results show that the sfn adapter can properly insert mip into transport stream and the time to be delayed in sync system can be correctly calculated and carried out with fifo 在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个单频网适配器进行了仿真。
It is the first time that driving chip used by pdp is applied to the fed panel . by adopting the new ic and the novel driving method , the developed grey scale modulator achieve high flexbility , stability and high integration . the circuit system includes cyclonetm fpga from altera and stv7610 from st microelectronic . with the capability of generating two kinds of modulating waveform , it has the advantages of flexible configuration , high display - quality , high integration and low cost . fpga design is based on the quartus platform . data transforming and the system controlling are achieved by using single fpga 基于altera公司cyclone系列fpga和st公司stv7610驱动芯片设计的fed显示器的灰度调制电路系统可以支持两种调制波形,具有配置灵活,显示性能好等优点,其集成度为原有系统的三倍,且造价更低廉;基于quartusii软件平台进行了fpga的系统开发与优化,采用单片fpga完成了全部的数据转换和系统控制功能, fpga的可编程特性使系统的设计具有充分的灵活性和可扩展性。
The logic design of interface circuit is realized in verilog hardware description language ( hdl ) . function simulation is finished by modelsim software . after the synthesis , placing , routing and obtaining delay information by develop tool quartus ii4 . 0 , timing simulation is accomplished by modelsim software 接口电路的逻辑设计采用硬件描述语言veriloghdl ,先借助modelsim软件进行功能仿真验证,在quartusii4 . 0的集成开发环境中完成综合、布局布线并提取元器件和网线上的实际延迟信息后,再借助modelsim软件进行时序仿真验证。
At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language , and its ip core is also achieved which is used not only in the satellite navigation position system , but also in the long pn code dsss system . ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project , and the technology has the definite theory and practice significance 此外还应用altera公司的最新的fpga开发工具quartusiiv5 . 1 ,采用了国际标准的硬件描述语言? vhdl语言,对数字差动匹配滤波器和传统匹配滤波器算法予以实现,开发了该算法的软ip核,可以对所应用的扩频码长度, a / d采样后的数据量化阶数,所用扩频码等可进行随意改写。
The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl 在innoveda的visualhdl设计平台上用hdl语言完成了设计输入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler进行了基于alterafpga库的网表综合，最后将edif网表输入altera的布局布线工具quartus中进行了布局布线，将生成的sdo文件反标到modelsim仿真器中进行了时序仿真，该设计的成功，再一次表明了hdl设计方法的正确性和有效性。
This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15 该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。
Although many achievements have been acquired in oled structure material , production technology , drive methods , oled technology is just at the beginning , oled has given an equal chance for every company and country , and it is very important for our country to develop displaying technology of our own . the research direction of oled is managing to improve the device lifetime , at the same time found a perfect production technological flow and the global standard production mode . it is still a arduous mission that we want to live up to a batch production of oled displays in the future some years . active matrix organic light emitting diode ( am - oled ) adopts a circuit structure based on matrix addressing , and its driving circuit includes pixel driving circuit and peripheral driving circuit 在文中,首先,分析和研究了有源oled的像素驱动电路,阐述了amoled显示屏及其周边驱动电路的结构和原理;其次,提出了qvga分辨率的有源oled显示屏列电极数据引线的分块( block )方法,确定屏上驱动电路所需要的控制信号之间时序关系和幅值要求;最后,以fpga控制器的设计为核心,对外围控制ic进行了具体设计,建立控制器电路模块模型和算法流程,通过quartus软件对其内部的各个电路模块进行综合设计和仿真,得到了正确的仿真波形,完成了分辨率为qvga ( 320 3 240 )的amoled专用驱动电路的设计。
In the logic design , the fundamentals and characteristics of ieee std . 1149 . 1 specification and usb protocol are introduced first of all . according to altera ’ s fpga cyclone , it analyzes the architecture and jtag instructions of boundary scan test ( bst ) . then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software 在接口逻辑设计中,首先分析ieee1149 . 1标准和usb协议,理解边界扫描测试和usb数据传输的工作方式,然后针对altera公司的fpga器件cyclone ,通过分析它的边界扫描测试结构和各种jtag指令,研究它的编程过程和编程特点,并提出设计方案。
According to the function of test platform , the test platform is partition into a few modules . those modules are designed with verilog hdl and the key problems are discussed in details . the verilog codes for transmit and receive end of test platform are simulated under quartus ii 5 . 0 ise , and debugged by downloading the verilog programs into ep1s25f780c and ep1s80b956c6 developing kits 在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个窄带ldpc解码-误码测试平台进行了仿真并将发端和收端的verilog程序分别下载到altera的ep1s25f780c和ep1s80b956c6开发实验板进行调试。
