Integrates various ip cores ; generally includes mpu , mcu , analog ip core , digital ip core , interface circuit , and ram or rom etc . 2 . large in scale , usually exceed one million gates , even to 10 million gates 2 .信号完整性问题,主要包括电源压降和信号串扰两个方面,出现这类问题的设计,往往功能仿真都没有问题,但流片后却不能正常工作。
Based on researching viterbi decoding algorithm , i design viterbi decoder on fpga using quartusii design platform of altera to design vhdl program , synthesis , simulate function logic and simulate time logic 本设计在viterbi算法研究基础上对viterbi译码器进行fpga设计,采用altera公司的quartusii开发工具为系统开发平台,在此平台上进行vhdl设计、综合、功能仿真和时序仿真。
By the top - down way , the design was divided into several modules according to their functions , which were characterized respectively . meanwhile , behavior description , rtl function simulation and logic synthesis were carried out 在充分了解驱动电路系统的基础上,采用“自上向下”的设计方法将其划分为几个功能模块,并对它们分别进行了行为描述、 rtl功能仿真、逻辑综合。
After a series of functional and time delay simulations , the design proved to be feasible and effective . the application indicates that the scheme is reasonable and the pxi - bus counter module meets the requirements of the design 本文对pxi计数器的各项功能进行了功能仿真和时序仿真,并对其进行了调试和测试,测试结果表明:模块设计方案合理、各项功能与指标均满足设计要求。
The simulation results are all in accordance with the theory analysis , some even better than the theoretical specification . the basic principle of discrete pulse frequency modulation on step - up dc / dc converter is testified , and this effort accumulates more experience to design 在完成电路原理分析与电路设计的基础之上,应用eda软件hspice对各个子电路模块和整体电路进行了功能仿真及量化模拟,仿真结果均达到或优于预定指标。
Then describes the 4 function modules in vhdl , the vhdl programs have passed compile and debug in maxplus ii , the results of function simulation and timing simulation all prove that the design is correct , at last , maxplus ii generates a netlist file which can be download into chip 然后使用vhdl硬件描述语言对四大功能模块进行描述，在maxplus环境下编译、调试通过，功能仿真和时序仿真结果证明设计正确，最后生成可下载的网表文件。
Rom megafunction block of ecg database is custom - made with quartusii as input data . filter coefficient is designed with fdatool in matlab . hardware model of fir filter ordering 16 is designed with dsp builder and function simulation is executed 论文利用quartusii定制出心电信号数据rom宏功能块以作为输入数据;采用matlab中fdatool设计工具设计出滤波器系数;再用dspbuilder技术对16阶fir低通滤波器进行了硬件模块设计,并进行了功能仿真。
Designing pte , with the architecture of amcc np3400 as a source reference . adding a scheme to this design , which is in order to ensrue forwarding sequence of packets . doing function simulation for the design of pte , with emphasis on this scheme 2 、以np3400网络处理器为基本参考模型，对pte模块进行了详细的设计和分析，在此基础上，讨论了ip数据包在并行处理过程中逆序的问题，在pte的设计中加入了避免ip包逆序的机制，并做了设计模型的功能仿真和相关分析。
( 2 ) basing on mc - jacobi algorithm , the dissertation designs evd hardware diagram . the dissertation does function simulation and timing simulation after coding by vhdl which is one of description language for rtl . making a model for real testing , the dissertation applys mc - jacobi algorithm into fpga on the demo board ( 2 )本文给出基于mc - jacobi算法的evd模块框图,采用vhdl语言进行rtl级描述,并进行功能仿真和时序仿真;在建立fpga硬件测试模型后,在开发板上进行硬件测试。
Chapter 5 gives the design illumination of the rs coder and decoder based on fpga . then it gives the integrated results for realization design of the rs ( 31 , 15 ) error - correcting code . after that , it gives the functional and layout simulation results for the limited field multiplier , divider , rs coder and rs de - coder 第五章给出了基于fpga实现的rs编码器和译码器设计说明, rs ( 31 , 15 )纠错码设计实现的综合结果,有限域乘法器、除法器、 rs编码器、 rs译码器的功能仿真和布局布线后仿真结果,最后总结主要的调试经验。
