Be careful , because if you need to insert data in sorted order , you may require a more complicated data structure with poor locality of reference , leading to cache misses and page faults 注意，因为如果需要按排序顺序插入数据，则可能需要具有较差引用地址的更复杂的数据结构，从而导致缓存未命中和页错误。
The performance is improved significantly . the average ipc speedup is 6 . 9 % . 3 . prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses 3 .通过对指令cache和数据cache失效行为的分析,提出一种预取策略? ?结合访存失效队列状态的预取策略。
This paper proposes a complementary novel idea , called minitasking to further reduce the number of cache misses by improving the data - it temporal locality for - it multiple concurrent queries 针对这样的现象，本文提出了一个称为minitasking的新思想，能够有效地提高多个并行查询中数据的时间局部性，从而进一步减少cache miss的数目，提高查询性能。
Cache misses and page faults missed cache hits , on both the internal and external cache , as well as page faults going to secondary storage for program instructions and data slow the performance of a program 缓存未命中不论出现在内部缓存中，还是出现在外部缓存中，都会降低程序的性能；而页错误由于会转到二级存储中获得程序指令和数据，也会降低程序的性能。
This paper introduced a much more precise sampling method using cpu hardware performance counters ( chpc ) to provide cpu data like instruction cycles , cache misses , branch prediction , and so on , and given detail scene of software status 摘要引入了基于cpu硬件性能计数器的性能数据采集和分析方法，从软件运行时刻的细粒度参数入手分析软件运行时刻的性能表现，从而更为准确地反映系统实际的动态运行状态。
Our data discloses that the hash - table and dynamic tree splitting operations used in crafty have caused huge l3 cache misses which at last bring in large scalability penalties . they consume 35 % ~ 50 % of the running time on our 4 - way system . by comparison , similar functions of prbfm only cost about 20 % running time 我们的试验数据表明crafty中哈希表操作和动态分裂树操作导致的l3cachemiss成为其多线程程序下的性能瓶颈,导致了极大的扩展性问题,在我们4路和16路的并行系统上,这些操作的时间占到了程序运行总时间的35 % ~ 50 % 。
These qualities make it ideal for things like on - line transaction processing oltp , business intelligence , enterprise resource planning , and other large and hyphenated , function - rich , database - enabled , multi - user , multi - tasking jobs with high cache miss rates - including web serving 这些特性使rs64芯片非常适合一些系统，例如联机事务处理（ oltp ） 、商业智能、企业资源计划（ erp ）以及其他一些大型的、功能强大的、具有多用户和多任务而缓存命中率很低的系统，其中包括web服务。
Adaptive stack cache with fast address generation policy decouples stack references from other data references , improves instruction - level parallelism , reduces data cache pollution , and decreases data cache miss ratio . stack access latency can be reduced by using fast address generation scheme proposed here 该方案将栈访问从数据高速缓存的访问中分离出来,充分利用栈空间数据访问的特点,提高指令级并行度,减少数据高速缓存污染,降低数据高速缓存失效率,并采用快速地址计算策略,减少栈访问的命中时间。
