This means that high - speed , high - level circuits can “ talk to ” low - levelcircuits through the common impedance of the negativesupply line 这意味着:高速,高电平的电路,通过负压供电线,可以和低电平的电路"对话"
The host changes the data line only when the clock line is low , and data is read by the device when clock is high 只有当时钟线为低的时候，主机才可以改变数据线（也就是将数据写入到数据线） 。数据将在时钟为高电平的时候被设备读取。
Jedec ? the voltage level at an output terminal with input conditions applied that , according to the product specification , will establish a high level at the output 根据产品技术规范，随加到输入端的情况在输出端的电平，将在输出端建立一个高电平。
Jedec ? the current into the output terminal with input conditions applied that , according to the product specification , establishes a high level at the output 按加到输入端信号的情况，电流流进一个输出端，并按照产品的技术规范，在输出端建立一个高电平。
After the stop bit is received , the device will acknowledge the received byte by bringing the data line low and generating one last clock pulse 只有当时钟线为低的时候，主机才可以改变数据线（也就是将数据写入到数据线） 。数据将在时钟为高电平的时候被设备读取。
Uses 4 gaas power double amplifier module . plug - in level adjustment and slope adjustment for each way are on the back panel , comvenient to use 4个高电平素出采用4个砷化镓功率倍增放大模块输出，每路独立的电平调整插件式和斜率调整插件式在机箱背板上，使用方便。
Acquisition of the fuse alarm digital variables : during idle , repeat acquired the 120 routes 48 analog data , process sample statistic for each rote acquired active - high 熔丝报警开关量信息的采集：在idle时候循环采集120路开入数据，对各路采到的实时高电平次数进行样本统计。
Note : a minimum is specified that is the least positive value of high - level input voltage for which operation of the logic element within specification limits is to be expected 注：在限定的工作条件下，规定的最小输入电压是极不容易保证逻辑单元所期望的高电平输入电压的最小正电压值。
On the contrary , in conventional pwm ’ s the pulse cycle is kept constant , but the pulse width is adjusted with the modulated signal . pwm has a numbers of applications ranging from industrial control to switch power 本文中的脉冲宽度调制是在脉冲频率变化,而将脉冲的高电平宽度固定,同样使脉冲的占空比发生变化以达到调制的目的。
The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high , then , without regard to the serial input , the data entered at a is at output qa , data entered at b is at qb , and so forth , following a low - to - high clock transition 表2中第三行表示计数器的同步平行的加载，和表明如果s1和s0为高电平,那么它就不是连续输入，在时钟由低向高跳变后，在a端的数据输入则在qa端输出，在b端的数据输入将在qb端输出，等等。
