The time division circuit and latch counter are integrated in one chip of programmable logic device , which makes the size greatly decreased 同时采用cpld芯片实现了时间分割电路和计数锁存电路,有效地减小了电路体积。
High ? speed synchronized latch circuit and special clock driver are used , which adapt to the requirement of quick data - transformation with high accuracy and low power 采用高速同步锁存电路和特殊结构的时钟驱动电路,在保证精度和功耗设计要求上,实现数据快速转换。
In this paper design of some circuit including in a / d circuit is also analyzed , such as front analog circuit , sample clock circuit and data flip - latch circuit 同时对高速转换器件及转换电路中包括前端模拟电路、采样时钟、后端数据锁存等辅助电路设计进行了分析。
3 scan controlling card the same kind of circuitry board which compatible outdoor one in fourth scan , one in second scan and the whole static state work way 4 3控制卡：采用全锁存静态恒流工作方式，在提高亮度的同时降低系统发热，在扼制系统电流波动同时有效地控制色温。
Controlling system is composed of drive circuit , locking memory , shift register . temperature compensating circuit and drive power circuit are also needed 控制系统是由驱动电路、锁存器、移位寄存器等组成，此外还需要温度补偿电路和驱动电源电路，本文对控制系统进行了详细的论述。
This happens because the index locks or latches within the database such as those surrounding the transaction log until the application is using a partitioned database 发生这一问题的原因在于数据库内的索引锁定或锁存（例如事务处理日志周围的索引锁定或锁存） ，直到该应用程序使用分区数据库为止。
Port c is also used in mode 1 operation - not for data , but for control or handshaking signals that help operate either or both port a and port b as strobed input ports 我觉得翻成“模式1选通输入”比较好一点，而010698 , 010700翻成了“模式一触动式输入” ， 010750 “模式1锁存输入” ， 010820翻成了“模式1滤波输入” 。
The dac consists of analog circuit blocks and digital circuit blocks , so it is a mixed signal circuit . because the digital part is simple comparatively , we use the same method as analog part to design it 采用模块化的设计方式实现数据快速转换,主要包括电流源矩阵模块、锁存模块、译码模块、带隙基准电压源模块及电流开关网络等电路模块。
The four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data which come from the six encorders are totally transacted in the fpga chip . the final data are sent to the pc through the serial interface of the fpga 坐标测量仪的六个编码器所传出的数据完全在fpga芯片中进行细分、辨向、计数以及锁存传输处理,最后所得的数据以串行通讯的方式传送到pc机。
This section addresses the timing relationships between transitions of one or more input signals that are necessary to ensure device functionality and applies only to sequential - logic devices ( e . g . , flip - flops , latches , and registers ) 本节为一个或更多输入信号之间的时序关系提供寻址，这些输入信号是使器件发挥作用的必须信号，并且只应用于顺序逻辑器件（比如触发器、锁存寄存器和寄存器） 。
